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| Freescale Semiconductor Advance Information Document Number: MC34920 Rev. 2.0, 1/2007 2.8 (Typ) Quad H-Bridge Motor Driver The 34920 is a multifunctional analog ASIC. The 34920 integrates two circuits, four H-bridge drivers, a reset circuit in a single IC, and two DC/DC switching voltage regulators. Input voltage is 21 V to 42 V DC. Each motor of the two driver blocks can be configured as either a DC motor driver with pulse width modulation (PWM)-control or a single bipolar step motor driver. In step motor mode, both drivers are capable of being operated in the quarter step mode. In DC motor mode, both bridges in a driver are in parallel, providing 2.4 A of drive current. In step motor mode, each bridge in a driver drives one phase. Each phase is driven with a bipolar current mode drive. Features * Individual Thermal Limit Protection * User-Selectable Motors: 2 DC Motors (2.4 A / Motor), 2 Step Motors (W1-2 Phase Control), 1 DC Motor and 1 Step Motor * 2 Buck Regulators (Switching @ 200 kHz) * VV2 Output Voltage Is Programmable to 10 V to 15 V DC (Externally Set) * Low-Voltage Detection Reset (VV1 and VVB+) * Pb-Free Packaging Designated by Suffix Code EI VVB+ VV1 + 34920 H-BRIDGE MOTOR DRIVERS FN SUFFIX EI SUFFIX (PB-FREE) 98ASB42598B 44-PIN PLCC ORDERING INFORMATION Device MC34920FN/R2 MC34920EI/R2 Temperature Range (TA) -40C to 125C Package 44 PLCC VV2 + 34920 V1_FB VB+ V1_SWITCH V2_SWITCH V2_FB DR1A DC MOTOR MCU RESET SDI SCLK CS DR2A DR1B DC MOTOR DR1PWM DR2PWM GND CP1 CP2 VB DR2B VVB+ + Figure 1. 34920 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2007. All rights reserved. BLOCK DIAGRAM BLOCK DIAGRAM V1_SWITCH V2_SWITCH V1_FB V2_FB CP1 CP2 VB+ V1 Regulator Oscillator V2 Regulator Boost Voltage Generator VB+ VB DR1A1 DR1B1 DR1SENSE1 RESET RESET DR1A2 DR1B2 DR1SENSE2 Control Logic-PWM Drive CS SCLK SDI DR1PWM DR2PWM Serial Input Port DR2A1 DR2B1 DR2SENSE1 DR2A2 DR2B2 DR2SENSE2 Figure 2. 34920 Simplified Internal Block Diagram 34920 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS DR1SENSE2 DR1SENSE1 20 DR2PWM DR1PWM DR1A2 DR1B2 DR1B1 DR1A1 19 GND 28 27 26 25 24 23 22 21 18 GND VB+ GND VB+ VB+ DR2B2 DR2SENSE2 DR2A2 VB+ V2_SWITCH DR2_MODE V2_FB GND 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 17 16 15 14 13 12 11 10 9 8 7 GND VB+ VB+ DR2B1 DR2SENSE1 DR2A1 VB+ V1_SWITCH DR1_MODE V1_FB GND SCLK VB RESET GND VCC CS Figure 3. 34920 Pin Connections Table 1. 34920 Pin Definitions Pin Number 1 2 3 4 5 6, 7, 17, 18, 28, 29, 39, 40 8 9 10 11, 15, 16, 23, 30, 31, 35 12 13 14 19 20 Pin Name VB CP2 CP1 RESET VCC GND V1_FB DR1_MODE Formal Name Output pin to VVb Capacitor to CP1 Capacitor to CP2 Reset Output VCC Supply Voltage Substrate Ground V1 Regulator Feedback Input Mode Select for Driver 1 Pin to connect to VVb capacitor. AGND GND Definition SDI CP2 Pin for boost generator switch capacitor. Pin for boost generator switch capacitor. Active low Reset output. VCC power input for internal use. The 34920 accepts either 3.3 V 10% or 5.0 V 5% for its logic voltage. Ground connections for digital IC circuitry. Voltage feedback for the V1 regulator. Selects operational mode of Driver 1; Step = 1 / DC = 0. Switching output for V1 regulator. High-voltage supply for motors and regulators. Motor driver output. Current sense for current mode. Motor driver output. Motor driver output. Current sense for current mode. V1_SWITCH Internal MOSFET Source for V1 Regulator VB+ DR2A1 DR2SENSE1 DR2B1 DR1A1 DR1SENSE1 VB+ (Bulk) Supply Voltage Driver 2, Bridge 1, Output A Driver 2, Bridge 1, I Sense Driver 2, Bridge 1, Output B Driver 1, Bridge 1, Output A Driver 1, Bridge 1, I Sense CP1 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 34920 Pin Definitions (continued) Pin Number 21 22 24 25 26 27 32 33 34 36 37 38 41 42 43 44 Pin Name DR1B1 DR1PWM DR2PWM DR1B2 DR1SENSE2 DR1A2 DR2B2 DR2SENSE2 DR2A2 Formal Name Driver 1, Bridge 1, Output B Driver 1 PWM Input Driver 2 PWM Input Driver 1, Bridge 2, Output B Driver 1, Bridge 2, I Sense Driver 1, Bridge 2, Output A Driver 2, Bridge 2, Output B Driver 2, Bridge 2, I Sense Driver 2, Bridge 2, Output A Motor driver output. Definition PWM input for Driver 1. Used only when DR1_MODE pin = 0. PWM input for Driver 2. Used only when DR2_MODE pin = 0. Motor driver output. Current sense for current mode. Motor driver output. Motor driver output. Current sense for current mode. Motor driver output. Switching output for V2 regulator. Selects operational mode of Driver 2. Step = 1 / DC = 0. Switch output for V2 regulator. Serial input register serial data input. Serial input register clock. Serial input register chip select input. Active low. Ground connection for analog circuitry. V2_SWITCH Internal MOSFET Source for V2 Regulator DR2_MODE V2_FB SDI SCLK CS AGND Mode Select for Driver 2 V2 Regulator Feedback Input Serial Port Data Input Serial Data Port Clock Serial Data Port Chip Select Analog Ground 34920 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS VB+ Supply Voltage VCC Voltage Bridge Output Current Maximum Voltage on RESET ESD Voltage (2) (1) Symbol Value Unit VVB+ VCC(MAX) IOUT VMAXRST VESD1 VESD2 45 7.0 1.5 VCC - 0.5 1000 100 V V A V V Human Body Model Machine Model THERMAL RATINGS Storage Temperature Operating Ambient Temperature Operating Junction Temperature Power Dissipation (TA = 25 C) Pin Soldering Temperature (4) (5) (3) TSTG TA TJ PD TSOLDER RJA -40 to 175 0 to 70 135 2.0 220 37 C C C W C C/W Thermal Resistance, Junction to Ambient Notes 1. RESET is an open drain (open collector) output with an internal pull-up resistor. 2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). 3. 4. 5. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. RJA is dependent on customer application and PCB layout. 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 21 V VVB+ 42 V, TA = 10C to 55C, TJ max = 135C, VCC = 5.25 V max unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under typical conditions unless otherwise noted. Characteristic POWER INPUT VVB+ Supply Voltage VVB+ Standby Current VVB+ = 42 V, ICC Load = 5.0 mA, No Serial Clock, No Motor Driver, No Load on VV2 CMOS LOGIC LEVEL (6) Symbol Min Typ Max Unit VVB+ IVB+ 21 - 42 V mA 1.0 14 55 Input Current, High-Voltage State Input Current, Low-Voltage State Input Low Input Voltage State VCC + 3.3 V 10% VCC + 5.0 V 5% Input High-Voltage State VCC + 3.3 V 10% VCC + 5.0 V 5% V1 AND V2 VOLTAGE REGULATORS Regulator Output Voltage Regulator Thermal Shutdown Junction Temperature Regulator Thermal Junction Temperature Overcurrent Detect Level (Peak) for IV1_SWITCH Overcurrent Detect Level (Peak) for IV2_SWITCH Short Circuit Detect Level (Peak) for IV1_SWITCH In Soft Start and Foldback Modes Short Circuit Detect Level (Peak) for IV2_SWITCH In Soft Start and Foldback Modes V1 Switching MOSFET on Resistance Full On, Typical Value @ TJ = 25C V2 Switching MOSFET on Resistance Full On, Typical Value @ TJ = 25C Regulator Feedback Input Internal Reference Value of 2.50 V 2% Turn-Off Regulator VV1 Output / VV2 Output = 0 V IIH IIL VIL - -170 0.1 -0.1 170 - A A V - - VIH 2.1 3.3 - - 0.8 1.5 V - - - - VOUT TJ (SHUTDOWN) TJ (ENABLE) IOC_V1 IOC_V2 ISC_V1 -4.0% 155 135 1.5 2.5 Nom - - 2.0 3.25 +4.0% 175 155 2.5 4.0 V o o C C A A A 0.75 ISC_V2 1.75 RDS(ON)V1 - RDS(ON)V2 - VV1_FB, VV2_FB VOFFV1_FB, VOFFV2_FB 1.25 1.75 A 2.25 2.75 2.0 - 0.75 - V - 2.5 - V 3.0 - - Notes 6. Applicable to all logic level input signals. Inputs are to be designed to accept 3.3 V logic levels and be +5.0 V tolerant. 34920 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 21 V VVB+ 42 V, TA = 10C to 55C, TJ max = 135C, VCC = 5.25 V max unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under typical conditions unless otherwise noted. Characteristic Voltage Overshoot External VCC Load Current from 0.01 to 0.500 A, tRISE > 100 ns Load Ripple 0.5 A maximum VBOOST GENERATOR Charge Pump Output Voltage ILOAD = 1.0 mA BIPOLAR CURRENT REGULATED STEP MOTOR DRIVE SYSTEM Peak Step Motor Current, Phase A or B Motor Not Stalled Maximum Allowable Voltage Drop Across Any H-Bridge Switch ILOAD = 0.6 A (from Output to GND) or ILOAD = 0.6 A (from VVB+ to Output) Comparator High Threshold Voltage CURR_I0_PHASEX=0, CURR_I1_PHASEX=0 Comparator Medium Threshold Voltage CURR_I0_PHASEX=1, CURR_I1_PHASEX=0 Comparator Low Threshold Voltage CURR_I0_PHASEX=0, CURR_I1_PHASEX=1 VOOFF Output Leakage Current for Step Motor Driver Outputs VOOFF = 5.0 V Step Motor Driver Thermal Shutdown Junction Temperature Step Motor Driver Thermal Enable Junction Temperature Single MOSFET Typical Value @ TJ = 25C DC MOTOR DRIVE SYSTEM Maximum Allowable Voltage Drop Across Any H-Bridge Switch ILOAD = 0.75 A (from Output to GND) or ILOAD = 0.75 A (from VVB+ to Output) (Using 2 H-Bridges in Parallel) Peak DC Motor Driver Current Motor Not Stalled (Using 2 H-Bridges in Parallel) DC Motor Overcurrent Threshold (7) Motor Stalled (Paralleled H-Bridges Used for DC Motor Drive) DC Motor Driver Sustaining Current Value Current Allowed to Sustain for a Minimum of 100 ms (OCT delay), Current Ripple 100 mA (Peak-to-Peak or Less) IDC_SUSTAIN 1.6 2.0 2.4 IDCMOTOR PEAK CURRENT IDCMOTOROCT 1.6 2.0 2.5 A VDROP - - 1.3 A - - 1.2 A V TJ (SHUTDOWN) TJ (ENABLE) RDS(ON) - 1.43 - IOOFF -1.0 155 135 0.1 - - 1.0 175 155 oC o Symbol Min Typ Max Unit - VOVRSHT - 5.0% - VOUTRIPPLE - 100 - mV VVB -VVB+ 10 - 14 V ISTEPMOTOR PEAK VDROP A - - 0.6 V - - 1.6 mV 450 550 650 mV 300 - 440 mV 105 - 255 mA VTH VTM VTL C Notes 7. Because the current clamp is applied to the top H-bridge transistors only, overcurrent protection applies to motor currents. But note that no short circuit protection exists against shorts from the DC motor outputs (DR1A1, DR1A2, DR1B1, or DR1B2 to substrate ground or to VB+. 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 21 V VVB+ 42 V, TA = 10C to 55C, TJ max = 135C, VCC = 5.25 V max unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under typical conditions unless otherwise noted. Characteristic Differential DC Motor Driver Output Voltage VVB++ Rising Monotonically from 0 V to 42 V (1.0 s < tR < 10 ms) OR VVB+ Falling Monotonically from 42 V to 0 V (1.0 s < tF < 10 ms) DC Motor Driver Thermal Shutdown Output Voltage IOH = 0.1 V DC Motor Driver Thermal Shutdown Junction Temperature DC Motor Driver Thermal Enable Junction Temperature Equivalent Resistance Using 2 H-Bridges in Parallel, Nom Value @ TJ = 25C RESET RESET High-State Output Voltage Symbol VDCMD Min Typ Max Unit V - - 4.0 VOH_DCM VVB+ 0.5 V TJ (SHUTDOWN) TJ (ENABLE) RDS(ON) - 0.73 - 155 135 - - - - 175 155 V oC o C VOH VCC - 0.5 V VOL - VIL - - VIH 2.1 3.3 VV1T1.9 VV1T+ 2.05 VVB+T13.5 VVB+T+ 13.5 16.6 20 15.4 16.5 2.23 2.35 2.08 2.2 - - - - - - 0.8 1.5 - 0.2 - - V IOH = -0.1 mA RESET Low-State Output Voltage V VV1_FB < VV1T+ Input Low Voltage State VCC + 3.3 V 10% VCC + 5.0 V 5% Input High-Voltage State VCC + 3.3 V 10% VCC + 5.0 V 5% RESET VV1_FB Low Threshold V V V Voltage at V1_FB RESET VV1_FB High Threshold V Voltage at V1_FB RESET VVB+ Low Threshold V VB+ RESET VVB+ High Threshold V VB+ 34920 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 21 V VVB+ 42 V, TA = 10C to 55C, TJ max = 135C, VCC = 5.25 V max unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under typical conditions unless otherwise noted. Characteristic SERIAL INPUT PORT TIMING Serial Clock Frequency SCLK High Width SCLK Low Width Delay CS Falling to First SCLK Rising Delay Last SCLK Rising Edge to CS Rising Data Valid to SCLK Set-Up Time Data Hold Time SDI Rise Time SDI Fall Time SCLK Rise/Fall Time CS Off-Time (tDHD + tDSU) V1 AND V2 VOLTAGE REGULATORS Clock Frequency Overtemperature V1 Duty Cycle V2 Duty Cycle BIPOLAR CURRENT REGULATED STEP MOTOR DRIVE SYSTEM Shoot-Through Delay Off-Time Current Blanking Time DC MOTOR DRIVE SYSTEM PWM Frequency TA = 25C Shoot-Through Delay Overcurrent Off-Time tDEAD fPWM - 15 10 20 180 40 21 350 70 ns s kHz tDEAD tOFF tBLANK 15 20 300 200 29 - 350 38 750 ns s ns fOP V1_DC V2_DC 175 35 80 200 37.5 82.5 225 40 85 kHz % % fCLK tCLH tCLL tCS-SCLK tSCLK-CS tDSU tDHD tRD tFD tRFC tNCS-OFF - 41.667 41.667 83.333 83.333 41.667 41.667 5.0 5.0 5.0 83.333 4.0 125 125 250 250 125 125 - - - 250 12 - - - - - - 10 10 10 - MHz ns ns ns ns ns ns ns ns ns ns Symbol Min Typ Max Unit tOC_OFF 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 21 V VVB+ 42 V, TA = 10C to 55C, TJ max = 135C, VCC = 5.25 V max unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under typical conditions unless otherwise noted. Characteristic RESET RESET Delay Symbol Min Typ Max Unit tDELAY 15 tPERSIST 10 tR - tF - 11 50 630 750 20 30 33 50 ms VV1_FB VV1T+ VCC Out-of-Tolerance Persistence Time RESET De-Asserted, VV1_FB < VV1TRESET Rise Time s ns 10% to 90% (8) RESET Fall Time ns 90% to 10% (8) Notes 8. Test circuit is 50 pF capacitor from RESET to GND. 34920 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS tCS-SCLK Tcs + SCLK TcsSCLK-CS t - SCLK nCS CS Data latched on rising edge of SCLK Data Latched on the rising edge of SCLK SCLK SCLK tDSU Tdsu tDHD Tend SDI SDI Bit Bit 11 Bit 2 Bit 2 Bit 3 Bit 3 Bit 4 Bit 4 Bit 55 Bit Bit Bit66 Bit 77 Bit Bit 88 Bit Bit Bit 99 Bit 10 Bit 10 Bit 11 Bit 11 Bit 12 Bit 12 Bit 13 Bit 13* SDI Stays at Last Value LSB LSB MSB MSB Time Time Figure 4. Serial Connectivity Diagram *SDI stays at last value Power On On Power VCC VCC 1.0V 1V Trip Level Trip VV1Tlevel VtVCC "Glitch" Response "Glitch" Response Power Off Power Off Trip Level VV1T Trip level VtVCC Short glitch below VV1T Short glitch below for less thanless than Tpersist VtVCC for tPERSIST RESET n RESET Undefined undefined undefined Undefined t DELAY Tdelay 15-50mS 15-50 ms (plus Tpersist delay) (plus t PERSIST) Tpersist delay t PERSIST Tdelay 15-50 mS t DELAY 15-50 ms (plus Tpersist delay_ (plus t PERSIST) t PERSIST Tpersist delay Figure 5. RESET Generation Timing Diagram (Assumes VVB+ > VVB+T+ During Entire Period) Assumes VB+ > VtVB+ during the entire period 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 34920 is a multifunctional analog IC that can be used in printer and scanner applications. It integrates two switching voltage regulator circuits, four H-bridge drivers, and a reset circuit in a single IC. All 34920 control lines are compatible with CMOS type 3.3 V and 5.0 V logic. and off. However, the Enable bit does not effect the V1 voltage regulator. The Enable bit will disable the V2 voltage regulator and disable all motor driver circuits. MOTOR DRIVERS The two motor drivers can be selectable as either a bidirectional DC motor driver, with PWM control and peak currents of 2.4 A, or a bipolar step motor driver, with average current levels of 183 mA and 550 mA per phase, and quarter step mode capability. In step mode, both drivers are capable of being operated in the quarter step mode. SWITCHING VOLTAGE REGULATOR CIRCUITS Two switching voltage regulators provide the following voltages from an unregulated input of 21 V to 42 V DC. Both are buck-type switching regulators using a MOSFET (internal to the 34920), current sense resistor (internal to the 34920), Schottky diode (external to the 34920), external inductor, and filter capacitor. * V1 Voltage Regulator - This regulator is programmable, has a duty cycle of 37%, and provides either 3.3 V (+5%/-4%) or 5.0 V (+5% / -4%) at a current of 10 mA (minimum) to 500 mA (maximum). * V2 Voltage Regulator - This regulator has a programmable output voltage (by means of an external resistor divider network) in the range of 10 V to 15 V 2% with a VB+ supply voltage range of 21 V to 42 V. The V2 voltage regulator is controlled by an Enable bit in the serial register that allows software to turn this regulator on RESET GENERATION The 34920 provides an output, RESET, that drives an external reset signal to the system microprocessor and / or the system digital logic IC. This signal is an active low logic level signal that is derived by monitoring the level of the VB+ and V1_FB pins. When RESET is asserted, either internally or from an external source, all 34920 motor driver outputs will be in their inactive states, and the serial input port will be loaded with the reset value. FUNCTIONAL INTERNAL BLOCK DESCRIPTION INPUT POWER SUPPLY (VVB+) The input voltage for the switching regulators and motor drivers. VVB+ has a voltage range of 21 V to 42 V. The digital controller initiates a serial transfer by pulling low the chip select line (CS). It then generates 13 clock pulses on the SCLK pin while presenting the serial data on the serial data input (SDI). The 34920 presents the data on SDI one setup time (t DSU) before the rising edge of SCLK. The data is held constant for the data hold time (t DHD) beyond the SCLK rising edge. The data is shifted into the 34920 on the rising edge of SCLK. The least significant bit (LSB) is the first to be shifted out of the 34920 on the rising edge of SCLK, followed by the remaining bits to the last of the 13 bits, which is the most significant bit (MSB). The CS line is then returned to a high state. The low-to-high transition of CS will load the data into the internal 34920 input register, where all the inputs are presented to their appropriate functions in a parallel fashion. Note The minimum off-time (CS signal equal to logic [1]) for the CS signal needs to be at least 1.0 t DSU delay + 1.0 t DHD delay. This will provide the time for the 34920 to clear the serial input data register (transfer the serial data in parallel to internal latches that use the data) and thereby avoid a data overrun condition and loss of data. See the serial input port timing data in the Dynamic Electrical Characteristics table, page 9. CMOS LOGIC LEVEL CMOS logic level specifications are described on page 6 of the Static Electrical Characteristics table. 34920 INPUT Table 5, page 13, describes the 34920 input specifications. SERIAL INPUT PORT The 34920 provides a serial input port for bit depth of 13 bits of input. This port provides an interface between the 34920 and the digital controller IC. This port is write-only. The interface consists of three signal lines: chip select (CS, active low), serial clock (SCLK), and serial data input (SDI). 34920 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 5. 34920 Input Specifications Name V1_FB VCC V2_FB CS SCLK SDI DRxPWM DRx_MODE Voltage feedback for the V1 regulator. VCC power input for internal use. The 34920 accepts either 3.3 V 10% or 5.0 V 5% for its logic voltage. Voltage feedback for the V2 regulator. Serial input register chip select input. Active low. Serial input register clock. Serial input register serial data input. PWM input for the DC motor driver for either Driver 1 or Driver 2. Selects mode of each motor driver. Step = 1/ DC = 0. Description The following inputs are through the Serial Input Register V2_Enable Enable bit to turn on and off the V2 regulator and the motor drivers. When low (= logic [0]), the V2 regulator and the motor drivers are turned off and the 34920 is placed in its lowest possible power state. V1 is not affected by the Enable bit. Second of two inputs that control the current level in the step motor Phase A winding (Driver 1 / Step Mode). First of two inputs that control the current level in the step motor Phase A winding (Driver 1 / Step Mode). Controls the direction of the current flow through Phase A of the step motor; i.e., logic [1] level causes conventional current flow from DR1A1 to DR1B1 (Driver 1 / Step Mode). Second of two inputs that control the current level in the step motor Phase B winding (Driver 1 / Step Mode). First of two inputs that control the current level in the step motor Phase B winding (Driver 1/ Step Mode). Controls the direction of the current flow through Phase B of the step motor. A logic [1] level causes conventional current flow from DR1A2 to DR1B2 (Driver 1 / Step Mode). Second of two inputs that control the current level in the step motor Phase A winding (Driver 2 / Step Mode). One of two inputs that control the current level in the step motor Phase A winding (Driver 2 / Step Mode). Controls the direction of the current flow through Phase A of the step motor. A logic [1] level causes conventional current flow from DR2A1 to DR2B1 (Driver 2 / Step Mode). Second of two inputs that control the current level in the step motor Phase B winding (Driver 2 / Step Mode). One of two inputs that control the current level in the step motor Phase B winding (Driver 2 / Step Mode). Controls the direction of the current flow through Phase B of the step motor. A logic [1] level causes conventional current flow from DR2A2 to DR2B2 (Driver 2 / Step Mode). DR1_CURR_I1_PHASEA DR1_CURR-I0_PHASEA DR1_DIR_PH_A DR1_CURR_I1_PHASEB DR1_CURR_I0_PHASEB DR1_DIR_PH_B DR2_CURR_I1_PHASEA DR2_CURR_I0_PHASEA DR2_DIR_PH_A DR2_CURR_I1_PHASEB DR2_CURR_I0_PHASEB DR2_DIR_PH_B 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION SERIAL INPUT PORT BIT DEFINITIONS Tables 6 through 9 define the bit definitions as they apply to the 13 bits of input that are brought into the 34920 through the serial input port. These signals are listed in bit order from LSB (first bit to be shifted in) to MSB (last bit to be shifted in). Table 6. Serial Input Port Definition for Step / Step Mode Name V2_Enable SDR2_CURR_I1_PHASEB SDR2_CURR_I0_PHASEB SDR2_DIR_PH_B Bit 1 2 3 4 Reset Value 1 1 1 0 Description Enable bit to turn on and off the V2 regulator and the motor drivers and place the 34920 in the minimum power consumption state. Second of two inputs that control the current level in the SDR2 step motor Phase B winding. One of two inputs that control the current level in the SDR2 step motor Phase B winding. Controls the direction of the current flow through Phase B of the SDR2 step motor. A logic [1] level causes conventional current flow from PH_B+ (source) to PH_B(sink). Second of two inputs that control the current level in the SDR2 step motor Phase A winding. One of two inputs that control the current level in the SDR2 step motor Phase A winding. Controls the direction of the current flow through Phase A of the SDR2 step motor. A logic [1] level causes conventional current flow from PH_A+ (source) to PH_A(sink). Second of two inputs that control the current level in the SDR1 step motor Phase B winding. One of two inputs that control the current level in the SDR1 step motor Phase B winding. Controls the direction of the current flow through Phase B of the SDR1 step motor. A logic [1] level causes conventional current flow from PH_B+ (source) to PH_B(sink). Second of two inputs that control the current level in the SDR1 step motor Phase A winding. One of two inputs that control the current level in the SDR1 step motor Phase A winding. Controls the direction of the current flow through Phase A of the SDR1 step motor. A logic [1] level causes conventional current flow from PH_A+ (source) to PH_A(sink). SDR2_CURR_I1_PHASEA SDR2_CURR_I0_PHASEA SDR2_DIR_PH_A 5 6 7 1 1 0 SDR1_CURR_I1_PHASEB SDR1_CURR_I0_PHASEB SDR1_DIR_PH_B 8 9 10 1 1 0 SDR1_CURR_I1_PHASEA SDR1_CURR_I0_PHASEA SDR1_DIR_PH_A 11 12 13 1 1 0 34920 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 7. Serial Input Port Definition for DC Motor / DC Motor Mode (9) Name V2_Enable Not Used Not Used Not Used Not Used Not Used DR2_DIR_DCM Bit 1 2 3 4 5 6 7 Reset Value 1 X X X X X 0 Description Enable bit to turn on and off the V2 regulator and the motor drivers and place the 34920 in the minimum power consumption state. Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Controls the direction of the current flow through the DC motor. A logic [1] level causes conventional current flow from DR2A1 (source) /DR2A2 (source) to DR2B1 (sink) / DR2B2 (sink). Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Controls the direction of the current flow through the DC motor. A logic [1] level causes conventional current flow from DR1A1 (source) / DR1A2 (source) to DR1B1 (sink) / DR1B2 (sink). Not Used Not Used Not Used Not Used Not Used DR1_DIR_DCM 8 9 10 11 12 13 X X X X X 0 Notes 9. DR1_MODE and DR2_MODE pins = logic [0] for DC motor drive for both drivers. 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 8. Serial Input Port Definition for DR1 = Step / DR2 = DC Motor Mode Name V2_Enable Not Used Not Used Not Used Not Used Not Used DR2_DIR_DCM Bit 1 2 3 4 5 6 7 Reset Value 1 X X X X X 0 Description Enable bit to turn on and off the V2 regulator and the motor drivers and place the 34920 in the minimum power consumption state. Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Controls the direction of the current flow through the DC motor. A logic [1] level causes conventional current flow from DR2A1 (source) /DR2A2 (source) to DR2B1 (sink) / DR2B2 (sink). Second of two inputs that control the current level in the SDR1DR1 step motor Phase B winding. One of two inputs that control the current level in the SDR1 step motor Phase B winding. Controls the direction of the current flow through Phase B of the SDR1 step motor. A logic [1] level causes conventional current flow from PH_B+ (source) to PH_B(sink). Second of two inputs that control the current level in the SDR1 step motor Phase A winding. One of two inputs that control the current level in the SDR1 step motor Phase A winding. Controls the direction of the current flow through Phase A of the SDR1 step motor. A logic [1] level causes conventional current flow from PH_A+ (source) to PH_A(sink). SDR1_CURR_I1_PHASEB SDR1_CURR_I0_PHASEB SDR1_DIR_PH_B 8 9 10 1 1 1 SDR1_CURR_I1_PHASEA SDR1_CURR_I0_PHASE SDR1_DIR_PH_A 11 12 13 0 1 1 34920 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 9. Serial Input Port Definition for DR1 = DC Motor / DR2 = Step Mode Name V2_Enable SDR2_CURR_I1_PHASEB SDR2_CURR_I0_PHASEB SDR2_DIR_PH_B Bit 1 2 3 4 Reset Value 1 1 1 0 Description Enable bit to turn on and off the V2 regulator and the motor drivers and place the 34920 in the minimum power consumption state. Second of two inputs that control the current level in the SDR2 step motor Phase B winding. One of two inputs that control the current level in the SDR2 step motor Phase B winding. Controls the direction of the current flow through Phase B of the SDR2 step motor. A logic [1] level causes conventional current flow from PH_B+ (source) to PH_B+ (sink). Second of two inputs that control the current level in the SDR2 step motor Phase A winding. One of two inputs that control the current level in the SDR2 step motor Phase A winding. Controls the direction of the current flow through Phase A of the SDR2 step motor. A logic [1] level causes conventional current flow from PH_A+ (source) to PH_A(sink). Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Controls the direction of the current flow through the DC motor. A logic [1] level causes conventional current flow from DR1A1 (source) /DR1A2 (source) to DR1B1 (sink) / DR1B2 (sink). SDR2_CURR_I1_PHASEA SDR2_CURR_I0_PHASEA SDR2_DIR_PH_A 5 6 7 1 1 0 Not Used Not Used Not Used Not Used Not Used DR1_DIR_DCM 8 9 10 11 12 13 X X X X X 0 VOLTAGE REGULATORS The 34920 contains two switching voltage regulators (see Figure 6). Both are buck-type voltage regulators using an internal switching MOSFET. The V1 regulator provides either 3.3 V or 5.0 V at +5% / -4% tolerance. The V2 regulator's output voltage, VV2, is programmable through the use of an external resistor divider network. The voltage tolerance on the VV2 output is 2% of the nominal voltage set point. The switching frequency of the V1 and V2 regulators is approximately 200 kHz. The V1 and V2 regulators are designed with a dual-mode current limit circuit. The current limit threshold is lowered during the power-on period to allow for a softer start-up, thereby reducing electrical stress in the external components. VVB+, the input voltage for the switching voltage regulators, ranges from 21 V to 42 V. To minimize the ripple current on VVB+, the V1 regulator and the V2 regulator switch out of phase. A boost voltage generator (VB generator), which acts as a single-stage charge pump, provides gate drive voltage for the switching regulators. It uses an external capacitor to store the charge. Output voltages VV1 and VV2 are set externally with a resistor (1% tolerance) divider network. Input voltages at V1_FB and V2_FB should be chosen to provide a feedback voltage, for the required output regulated voltage, to equal the internal regulator reference voltages of 2.5 V 2%. 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION VVB+ (21 V to 42 V) VB+ 34920 V1_SWITCH VV1 V1 Regulator V1_FB VB+ Oscillator V2_SWITCH VV2 V2 Regulator V2_FB ENABLE VVB+ (21 V to 42 V) VB Oscillator Vb Generator CP1 CP2 10 nF 50 V 22 F 25 V Figure 6. Voltage Regulator Functions VOLTAGE REGULATOR OUTPUT REQUIREMENTS Table 10 provides a listing of the output voltages and currents. Both switchmode converters operate at approximately 200 kHz 25 kHz. Table 10. Voltage Regulator Output Requirements Voltage Name VV1 VV2 (10) Minimum Voltage -4.0% of Nominal -2.0% of Nominal Maximum Voltage +4.0% of Nominal +2.0% of Nominal Load Range 10 mA Min, 500 mA Max DC 10 mA Min, 1.3 A Max DC (11) Notes 10. This voltage is programmable within a range of 10 V to 15 V via external resistors. The voltage tolerance around any set point is 2% of the nominal. 11. Maximum peak duration is 400 ms. The V1 and V2 regulators provide individual internal overtemperature sensing for protection. During an overtemperature event, when the device TJ is at or above TJ (SHUTDOWN) , the internal thermal protection circuit disables the drive outputs by driving all outputs to the zero current state until the device temperatures have dropped below the lower thermal threshold temperature TJ (ENABLE), at which time the driver is re-enabled. The V1 and V2 voltage regulators may be shut down by applying a voltage in the range of 3.0 V to 6.0 V to the respective V1_FB and V2_FB pins. This will result in the regulator output voltages to be equal to 0 V. OVERCURRENT PROTECTION Output voltages VV1 and VV2 are short circuit protected. The outputs respond to an overcurrent situation by limiting the internal switching duty cycle. This can be reset by removing the main supply to the chip or when the short circuit condition is removed. Refer to the respective IOC and ISC 34920 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION values for V1 and V2 voltage regulators on page 6 of the Static Electrical Characteristics table. phase from the V1 regulator to minimize ripple current on VB+. This converter is designed so that the current limit threshold is lowered during the power-on period to allow for a "softer" start-up, thereby reducing electrical stress in the external components. This limiting is required for their safe operation. The output voltage is variable with 2% precision, with a VVB+ supply voltage range of 21 V to 42 V. The exact voltage will be set externally with a resistor (1% tolerance) divider network. The V2_FB input voltage should be chosen, using external voltage divider resistors, so as to provide a regulator feedback voltage, for the required output regulated voltage, to equal the internal regulator reference voltages of 2.50 V 2%. Output current sensing is implemented by sensing the voltage across an internal sense resistor connected between VB+ and the drain of the internal MOSFET. Current is measured on a cycle-by-cycle basis. The purpose of this current sense is to prevent any damage to the 34920 and its associated external components. Note There is a V2_Enable bit in the Serial Communication Input register (bit 1). When this bit is set to logic [1], the V2 voltage regulator is enabled. When this bit = logic [0], the V2 voltage regulator is disabled. Refer to Tables 5 through 9, pp. 13-17, for a description of this bit. The V2_Enable bit will also disable the motor drivers. POWER-SAVING MODE OF OPERATION The V2 voltage regulator can be disabled via the serial interface by setting the V2_Enable bit (bit 1 - LSB) to a value of 0. This provides a reduction in the bias current provided by the V1 supply. V1 VOLTAGE REGULATOR Implementation of the V1 switching voltage regulator is accomplished through the use of an internal switch MOSFET, internal MOSFET current sense resistor, external Schottky diode, external inductor, and filter capacitor. The frequency of operation of this regulator is controlled by the internal clock, which is 200 kHz 25 kHz. The duty cycle (on-time) for this internal regulator clock is a fixed 37.5%. This regulator switches out of phase from the V2 regulator to minimize ripple current on VB+. The line regulation range is 21 V < VVB+ < 42 V. The load side regulation is specified on page 6 of the Static Electrical Characteristics table. This converter is designed so that the current limit threshold is lowered during the power-on period to allow for a "softer" start-up, thereby reducing electrical stress in the external components. This limiting is required for their safe operation. The voltage is set externally with a resistor (1% tolerance) divider network. The V1_FB input voltage should be chosen, using external voltage divider resistors, so as to provide a regulator feedback voltage, for the required output regulated voltage, to equal the internal regulator reference voltage of 2.50 V 2%. The V1 regulator is ideal for providing either 3.3 V or 5.0 V with a precision of +5% / -4%. Output current sensing is implemented by sensing the voltage across an internal sense resistor connected between VB+ and the drain of the internal MOSFET. Current is measured on a cycle-by-cycle basis. The purpose of this current sense is to prevent damage to the 34920 and its associated external components. VB GENERATOR The boost voltage generator circuit is a charge pump circuit using two external capacitors to provide the necessary voltage to drive internal 34920 loads. This circuit is driven at a frequency of 200 kHz 25 kHz. The VB generator is utilized exclusively by the 34920. There is no provision for external loading. Also, there is no disable feature for the VB generator. MOTOR DRIVE SYSTEMS The 34920 provides two motor drivers. Both drivers are mode selectable to be either a multi-current level bidirectional driver for bipolar step motors or a bi-directional DC motor driver with PWM control. The DR1_MODE (Mode1) and DR2_MODE (Mode2) pins select whether the appropriate motor driver will drive a step motor (pin = 1) or DC motor (pin = 0). Figures 7 and 8 depict the two motor configurations. V2 VOLTAGE REGULATOR The V2 switching voltage regulator is implemented as a buck regulator with an internal switch MOSFET, internal MOSFET current sense resistor, external Schottky diode, external inductor, and filter capacitor. The frequency of operation of this regulator is controlled by the internal clock, which is 200 kHz 25 kHz. This regulator switches out of 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION DR1PWM DR1_MODE VB+ 34920 DR1 DR1A1 DR1B1 DR1SENSE1 SDR1_DIR_PH A SDR1_CURR_I1 PHASEA SDR1_CURR_I0 PHASEA DR1_DIR_DCM Phase A H-Bridge Step Motor DR1A2 DR1B2 SDR1_DIR_PH_B SDR1_CURR_I1_PHASEB SDR1_CURR_I0_PHASEB Phase B H-Bridge DR1SENSE2 Figure 7. Simplified Step Application Diagram Showing 1 of 2 Step Drive Circuits 34920 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION DR2PWM DR2_MODE VB+ 34920 DR2 DR2A1 SDR2_DIR_PH A SDR2_CURR_I1 PHASEA SDR2_CURR_I0 PHASEA DR2_DIR_DCM + Phase A H-Bridge DR2B1 DC Motor DR2A2 Phase B H-Bridge SDR2_DIR_PH_B SDR2_CURR_I1_PHASEB SDR2_CURR_I0_PHASEB DR2B2 Figure 8. Simplified DC Application Diagram Showing 1 of 2 Motor Drive Circuits BIPOLAR CURRENT REGULATED STEP MOTOR DRIVE SYSTEM The drive circuitry is powered by the VVB+ supply voltage. For example, with external current sense resistors of 0.910 1%, the drive circuitry provides drive for a bipolar step motor at current levels of approximately 183 mA, 367 mA, and 550 mA. Current mode operation supports quarter stepping. This drive enters the fast current decay mode when both the CURR_I0_PHASEX and CURR_I1_PHASEX inputs are set to the logic [1] level. In fast current decay mode, any residual motor winding current is forced into the VVB+ supply rail when going to a zero current state from a non-zero current level. This forces the motor winding current toward zero as quickly as possible. For each of the two H-bridge drivers, controlled crossover delay, a blanking period, and internal overtemperature sensing are provided. The crossover delay is controlled to provide sufficient time for cross-conduction suppression. At no time will both the upper and lower output device on the same side of the H-bridge be allowed to conduct simultaneously. Also, following a turn-on event a blanking period is included to prevent false turn-offs owing to the initial turn-on current spike, which results from motor circuit capacitance. This drive has internal overtemperature sensing for protection. During an overtemperature event, when the device TJ is at or above TJ (SHUTDOWN), the internal thermal protection circuit disables the drive outputs by driving all outputs to the zero current state until the device temperatures have dropped below the lower thermal threshold temperature TJ (ENABLE), at which time the driver is re-enabled. Note During power-on the step motor driver circuit inhibits its outputs when VVB+ is at 4.0 V or greater until RESET is released. Likewise, during power-down the step motor driver circuit inhibits its outputs from the point when RESET goes low until VVB+ has dropped below 4.0 V. 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION DC MOTOR DRIVE SYSTEM This drive circuitry provides bi-directional drive to a DC motor via two inputs, DCM_PWM (an external pin, CMOScompatible input) and DRx_DIR_DCM (a bit in the serial input port; refer to Tables 7 through 9, pp. 15-17). This drive is powered from VB+. The DC motor control circuitry uses voltage mode control. To drive a DC motor the 34920 outputs DR2A1 and DR2A2 must be connected together externally, then connected to the DC motor "+" lead. Likewise, the 34920 outputs DR2B1 and DR2B2 must be connected together externally, then connected to the DC motor "-" lead (see Figure 8). This drive provides internal overtemperature sensing for protection. During an overtemperature event, when the device TJ is at or above TJ (SHUTDOWN), the internal thermal protection circuit disables the drive outputs by driving both outputs to the high state until the device temperatures have dropped below the lower thermal threshold temperature TJ (ENABLE), at which time the drive is re-enabled. The crossover delay must be controlled to provide sufficient time for cross-condition suppression. At no time can both the upper and lower output devices on the same side of the H-bridge be allowed to conduct simultaneously. Also, following a turn-on event a blanking period is included to prevent false turn-offs owing to the initial turn-on current spike, which results from motor circuit capacitance. Note During power-on the DC Motor Driver circuit inhibits its outputs when VVB+ is at 4.0 V or greater until RESET is released. Likewise, during power-down of the machine the DC Motor Driver circuit inhibits its outputs from the point when RESET goes low until VVB+ has dropped below 4.0 V. longer than the delay period of tDELAY and VVB+ is still less than VVB+T- . In this situation RESET will remain low until VVB+ is greater than VVB+T- , at which point RESET will be released immediately and there will be no delay period. If VVB+ passes through VVB+T+ during the tDELAY period, RESET will remain low until the end of the tDELAY period, which started at the time VV1_FB passed through the VV1T+ level. During power-down this output immediately asserts a logic low at the point when VV1_FB drops down to the trip point of VV1T- . Also, if VVB+ drops below VVB+T- and VV1_FB is still at or above VV1T- , RESET will be pulled low. RESET BEHAVIOR The following conditions describe the behavior of the RESET circuit. A Note on Terminology Assertion of RESET is defined as the RESET pin outputting a logic low voltage, and deassertion is when the pin is pulled up to the VCC voltage. On the power-up condition, RESET behaves as follows: * If 1.0 V < VV1_FB < VV1T+ or VVB+ < VVB+T+ , RESET will be asserted. Important If VV1_FB < 1.0 V, RESET is undefined. * If RESET is asserted owing to VV1_FB < VV1T- , then when VV1_FB rises monotonically from below VV1T- to above VV1T+ , RESET will de-assert after a duration of tDELAY. * If RESET is asserted owing to VVB+ < VVB+T+ and VV1_FB VV1T+ , then when VVB+ rises to the VVB+T+ level RESET will de-assert with no delay. The only case where a delay would be seen is if the time period from where VV1_FB rises to the VV1T+ level to the point where VVB+ rises to the VVB+T+ level is less than the tDELAY period. Then the delay in de-asserting RESET would be the remaining tDELAY time, thereby maintaining the full tDELAY period, between the time when VV1_FB reaches VV1T+ and the de-assertion of RESET, that is required for a reliable system reset. On the power-down condition, RESET behaves as follows: * If RESET is not asserted, and the VV1_FB voltage monotonically decreases to a value below the negativegoing threshold of VV1T- and remains below VV1T- for longer than tPERSIST (10 s to 30 s), RESET will be asserted. RESET will remain asserted while 1.0 V < VV1_FB < VV1T+ . If VV1_FB falls below 1.0 V, the RESET signal is undefined. * RESET will also be asserted when VVB+ decreases below the VVB+T+ level. This will occur even if the VV1_FB level is still above VV1T- . RESET FUNCTIONALITY The 34920 provides an output, RESET, that drives an external reset signal to the system microprocessor and/or the system digital logic IC. This signal is an active low logic level signal that is derived by monitoring the level of the VCC pin. This output is the equivalent of an open drain- (or open collector-) type output, with an internal 2.5 k pull-up to VCC. This output pin can be driven by other external sources and therefore the state of RESET must be monitored by the 34920. Note When RESET is asserted either internally or from an external source, all 34920 motor drive outputs will be in their inactive states, and the serial input port will be loaded with the "Reset Value" (refer to Tables 6 through 9). The V2 voltage regulator will be enabled. During power-up this output asserts a logic low level, and it monitors the V1 regulator output voltage and detects the point that it reaches VV1T+ . The output will then remain low for a delay of 15 ms to 50 ms before releasing to a high state. A second case is if VV1_FB is at or above VV1T+ for a period 34920 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION On the VV1_FB glitch condition, RESET behaves as follows: * If the VV1_FB supply falls below VV1T- and remains there for less than tPERSIST (10 s to 30 s), RESET will not be asserted. However, if the condition lasts longer than tPERSIST, RESET will be asserted for a duration of tDELAY. The 10 s-to-30 s persistence time specified in tPERSIST is for ESD rejection. The reset trigger will be a retriggerable one-shot, where the delay pulse will be 10 s to 30 s for the delay timeout. ESD IMMUNITY Refer to the Maximum Ratings table, page 5. OVERTEMPERATURE PROTECTION The 34920 implements overtemperature detection and shutdown functions. The overtemperature circuitry monitors the device's internal temperature and activates thermal shutdown circuitry when the temperature exceeds TJ (SHUTDOWN) (155C minimum, 175C maximum). The thermal shutdown condition is maintained until the die temperature falls below TJ (ENABLE) (135C minimum, 155C maximum). Each voltage regulator and motor driver circuit has its own individual shutdown circuit. ENVIRONMENTAL SPECIFICATIONS AMBIENT TEMPERATURE AND RELATIVE HUMIDITY Table 11 lists the temperature and relative humidity for operating and storage conditions for the 34920. Table 11. Ambient Temperature and Humidity Condition Operating Storage Temperature (C) 0 to 70 -40 to 150 % Relative Humidity 8.0 to 80 5.0 to 80 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 12. Step Motor Truth Table CURR_I0_ PHASEA 0 1 0 1 0 1 0 CURR_I1_ PHASEA 0 0 1 1 0 0 1 CURR_I0_ PHASEB 0 1 0 1 0 1 0 CURR_I1_ PHASEB 0 0 1 1 0 0 1 DIR_PH_A 0 0 0 X 1 1 1 IPH_A (mA) 550 367 183 Off -550 -367 -183 DIR_PH_B 0 0 0 X 1 1 1 IPH_B (mA) 550 367 183 Off -550 -367 -183 Table 13. DC Motor Drive System Truth Table DRx_DIR_DCM 0 0 1 1 DRxPWM 0 1 0 1 High-Side A On Off On On Low-Side A Off On Off Off High-Side B On On On Off Low-Side B Off Off Off On 34920 24 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS LOGIC VOLTAGE (VCC) AND RESET INTEROPERABILITY The 3.3 V or 5.0 V VV1 output voltage should feed back to the VCC input pin directly (see Figure 9) to ensure that the 34920 can be properly reset during a power-down situation. VVB+ (21 V to 42 V) VB+ If this typology is not the one implemented, the user needs to be aware that the VCC pin is not monitored for undervoltage. Only the V1_FB and VB+ pins are monitored for undervoltage. Thus, it is possible for VCC to be under voltage without the 34920 issuing a reset. 34920 VCC V1_SWITCH VV1 V1 Regulator V1_FB VB+ Oscillator V2_SWITCH VV2 V2 Regulator V2_FB ENABLE VVB+ (21 V to 42 V) VB Oscillator Vb Generator CP1 CP2 10 nF 50 V 22 F 25 V Figure 9. Voltage Regulator Functions 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 25 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below. FN SUFFIX EI-PIN PLASTIC PACKAGE 98ASB42598B ISSUE E 34920 26 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS FN SUFFIX EI-PIN PLASTIC PACKAGE 98ASB42598B ISSUE E 34920 Analog Integrated Circuit Device Data Freescale Semiconductor 27 REVISION HISTORY REVISION HISTORY REVISION 2.0 DATE 8/2006 DESCRIPTION OF CHANGES * * * Implemented Revision History page Converted to Freescale format and updated to the prevailing form and style Added EI Pb-FREE suffix 34920 28 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 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Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2007. All rights reserved. MC34920 Rev. 2.0 1/2007 |
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